The present invention concerns a numerically controlled oscillator in particular for a radiofrequency signal receiver, such as a GPS type receiver. Such an oscillator is intended to receive at one input a clock signal with a first frequency clocking the oscillator operations, and a binary word defined by several bits, and to provide at one output at least a signal with a frequency determined as a function of said binary word and the clock signal.
The output signal with a determined frequency is a signal which is basically a succession of rectangular voltage pulses wherein the width of the pulses and intervals between two pulses are not necessarily uniform over a given period of time. It should be noted that this output signal may be considered as a succession of bits in series taking the values 1 or 0 at each clock stroke as a function of the binary word imposed at the input of the oscillator. Of course, said oscillator may provide at its output more than one output signal each defined by a different succession of bits in series.
These numerically controlled oscillators are used inter alia in fields of applications where the environment is noisy. In a noisy environment, the signals used have to be extracted from the greatly disturbed radiofrequency signals while keeping a fine frequency resolution for the oscillators. These fields of applications are for example the cellular telephone or mainly radiofrequency signal receivers, such as GPS receivers.
In the case of radiofrequency signal receivers, the signals received are generally demodulated to extract the message from said radiofrequency signals. Numerically controlled oscillators are usually placed in demodulation loops of the correlation stages of such receivers. These oscillators allow signals to be supplied at a determined frequency or corrected for example to generate a replica of the carrier frequency of the received radiofrequency signals. This frequency replica is then multiplied in the correlation stage by the signals shaped in said receivers in order to be able to extract the useful signals.
In the case more precisely of GPS type receivers, a first numerically controlled oscillator is placed in the loop for generating carrier frequency replica of the received signal. A second numerically controlled oscillator is placed in the loop for generating the replica of the characteristic pseudo-random code PRN of the satellite to be tracked.
These GPS type radiofrequency receivers include in particular a receiving antenna for radiofrequency signals originating from satellites, a receiving and shaping stage for radiofrequency signals provided by the antenna, and a correlation stage receiving intermediate signals shaped by the receiving stage. The correlation stage is formed of several channels which each include a correlator. Each correlator thus includes the two numerically controlled oscillators described above.
Said receivers also include a microprocessor connected to the correlation stage and intended to calculate X, Y, Z position, speed and time data as a function of the data extracted, after correlation, from the GPS signals transmitted by the satellites. The data extracted from the GPS signals are the GPS message and pseudo-ranges. Four visible satellites are normally needed to determine the position, speed and local time for example.
It should be noted that the satellites, which are currently 24 in number in orbit around the Earth, transmit radiofrequency signals carrying ephemerides and almanac data messages which are used in particular to calculate position. These radiofrequency signals are formed of a first carrier frequency L1 at 1,57542 GHz on which are modulated the P-code at 10,23 MHz and the C/A PRN code at 1,023 MHz particular to each satellite with the GPS message at 50 Hz. Said satellites also transmit a second carrier frequency L2 at 1,2276 GHz on which are modulated the Pcode at 10,23 MHZ with the GPS message at 50 Hz. In civilian applications, only carrier frequency L1 with the C/A code is used by the terrestrial receivers for calculating, in accordance with the GPS message, the X, Y and Z position, speed and time.
The C/A PRN code (pseudo random noise) of each satellite, which is also called the Gold code, is a unique pseudo-random code for each satellite so as to be able to distinguish the signals transmitted by the satellites inside the receiver.
This pseudo-random PRN code is a digital signal which is formed of 1023 chips and which is repeated every millisecond. This repetition period is also defined by the term xe2x80x9cepochxe2x80x9d of the Gold code. It is to be noted that a chip takes values 1 or 0 like a bit. However, a chip (a term used in GPS technology) should be distinguished from a bit which is used to define a unit of data.
The Gold codes are defined for 32 satellite identification numbers which leaves a free choice for the specific code allocated to each additional satellite which will be put into orbit on one of the orbital planes. The GPS receivers generally include the data for these codes in a memory, as well as the estimated position of each corresponding satellite in orbit. Consequently, binary words relating to the code frequency of a satellite and to the estimated carrier frequency can be provided to the oscillators used in the demodulation loops to allow quicker locking onto the visible satellites.
By way of example, FIG. 1a shows schematically a numerically controlled oscillator of this type which is commonly used in radiofrequency signal receivers. Oscillator 5 receives at its input a phase binary word with Nb bits in parallel which is placed in an Nb-bit phase register 6. In demodulation loops, it is mainly phase offset binary words which are introduced into the numerically controlled oscillator. Register 6 supplies the stored number Nb of bits to a phase accumulator 7 which is clocked by a clock signal CLK. Output lines Nxe2x80x2b from accumulator 7 are connected to inputs of said accumulator so that output bits or binary signals in parallel on said lines are added to number Nb of bits at each clock stroke. Normally, the number Nxe2x80x2b of output bits is equal to number Nb of binary word bits. Lb bits outputting from the accumulator are directed to the microprocessor in particular to perform a real time phase calculation. A number Mb of binary signals are provided as output signals with a frequency determined by the oscillator. The number Mb of output bits does not need to be equal to all the Nb bits inputted into the oscillator. In most cases, only certain most-significant bits are used to define the output signals.
In most radiofrequency receiver applications, such as GPS receivers, reduction in power consumption has become a necessity. This reduction in power consumption is particularly essential when such receivers are incorporated in objects of small dimensions which include battery or accumulator power supply. Such objects are for example a watch or a portable telephone.
This power consumption of the receivers must not be too great in these small objects in order to avoid the battery of the object being changed too frequently or an energy accumulator having to be systematically recharged after short time periods. It is to be noted that the smaller the battery depending on the size of the portable object, the more necessary it is to design small electronic units for the GPS receiver integrated circuits. Moreover, the manner in which the signals are processed in said circuits to extract the GPS message and the pseudo-distances of each satellite picked up has to be taken into account.
The standard numerically controlled oscillator, described hereinbefore with reference to FIG. 1a, constitutes a significant part of the power consumption of the whole correlation stage of a radiofrequency signal receiver, such as a GPS receiver. This oscillator has to be sufficiently large to have a small frequency resolution. Clock frequency CLK is often greater than several megahertz depending on the sampled and quantified signals to be processed, which means that all the components of the oscillator operate at a very high frequency. This thus generates a high power consumption which is a major drawback of such standard oscillators.
Japanese Patent Application No. 8-338865 discloses a GPS receiver. A numerically controlled oscillator of the type described hereinbefore is mounted in this receiver for the purpose of reducing the number of components in the carrier frequency replica generating loop. In order to do this, it is proposed to add a most-significant bit to several least-significant bits in an adder. The most-significant bits are then kept in a register in order to be placed at the input of the adder for a subsequent adding operation. In this embodiment, a search table at the oscillator output is no longer necessary to generate the quarter-phase signals of the carrier frequency replica. The quarter-phase signals are supplied by two output signals of the oscillator through a XOR logic gate and by one of the two output signals through an inverter. The two oscillator output signals used are the two most-significant bits of the output signals. Despite the reduction in the number of the oscillator loop output components, there is no significant reduction in power consumption of the oscillator itself. This oscillator as a whole thus still operates at a very high clock frequency which is a drawback.
One object of the invention consists in providing a numerically controlled oscillator in particular for a radiofrequency signal receiver capable of reducing energy consumption as much as possible while overcoming the drawbacks of oscillators of the prior art. The small frequency resolution is kept equal to the oscillators of the prior art, but conversely, energy consumption is greatly reduced.
This object, in addition to others, are achieved by the aforecited numerically controlled oscillator in particular for a radiofrequency signal receiver, which is characterised in that it includes a first accumulation stage for a first number of most-significant bits of the binary word and a second accumulation stage for a second number of least-significant bits of said binary word, the first accumulation stage being clocked by the clock signal at the first frequency to supply the output signal at a determined frequency, while the second stage is clocked by a clock signal at a second frequency N times lower than the first clock frequency, a certain number of output bits or binary signals from the second stage being introduced at the input of the first stage every N cycles of the clock signal at the first frequency.
One advantage of the multiphase numerically controlled oscillator consists in reducing the energy consumption by only working for example half of the oscillator during N cycles of a clock signal at a first frequency. The resolution of this multiphase oscillator is not reduced with respect to a standard numerically controlled oscillator. This first clock frequency is of the order of several megahertz. Consequently, if half or more of the oscillator remains on standby during N clock strokes at the first frequency, this allows the energy consumption of the oscillator to be greatly reduced.
This multiphase oscillator is especially useful in a noisy environment as in the case of GPS type radiofrequency signals.
A certain number of most-significant bits of the binary word are introduced into the most-significant bit accumulation stage which operates at the first clock frequency. This part is the most important part of the oscillator to be able to keep the same frequency resolution as that of a conventional oscillator. The least-significant bits of the binary word are introduced into the least-significant bit stage which operates, at a second frequency N times lower than the first frequency. The influence of the least-significant bits has only a long term effect. Consequently, the output bits or binary signals from this accumulation stage multiplied by N are only introduced into the most-significant bit accumulation stage after N cycles of the first clock frequency.
N is a power of 2, i.e. N is preferably chosen to have a value 2m where m is an integer number greater than 0 to define a binary number. The value of N may be fixed for example at 16, which means that the second clock frequency is 16 times lower than the first frequency. The energy consumption of the multiphase oscillator can be evaluated as being approximately half of that of a conventional oscillator if the numbers of most-significant and least-significant bits are uniformly distributed in each accumulation stage.
The clock frequencies used in the receiver are adapted as a function of the frequencies of the received radiofrequency signals in order to clock several parts in an identical manner. This has the effect of also reducing the number of electronic elements in particular in the correlation stage and consequently the receiver""s energy consumption. Moreover, a reduction in energy consumption is achieved by converting or compressing the frequency of the radiofrequency signals going to the correlation stage.